00777nam a2200253 a 4500 BD-DhGUBL 20241112105902.0 150315m20142013ii a b 001 0 eng d 9788131794746 (NNC)5618455 DLC DLC BD-DhGUBL 23 621.3815 M3171d Mano, M. Morris Digital Design : with an Introduction to the Verilog HDL / M. Morris Mano, and Michael D. Cliletti. 5th ed. New Delhi : Pearson, c 2014. xv, 678 p. : ill. ; 25 cm. Includes index. Electronic digital computers Circuits Logic circuits Logic design Ciletti, Michael D. Joint author ddc BK 2061 2061 0 0 ddc 0 1 EEE GUBL GUBL REF 2015-03-10 1019.00 1 621.3815 M3171d 3020014723 2016-04-27 00:00:00 2016-04-24 1 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 30 54 621.3815 M3171d 3020014728 2025-01-02 12:45:04 2024-12-23 2 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 33 63 621.3815 M3171d 3020014729 2026-11-06 10:43:06 2026-11-04 3 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 25 53 621.3815 M3171d 3020014730 2026-09-13 12:13:59 2026-09-02 4 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 38 57 621.3815 M3171d 3020014721 2026-11-06 10:43:15 2026-11-04 5 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 38 69 621.3815 M3171d 3020014722 2026-11-13 09:00:38 2026-11-04 6 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 17 28 621.3815 M3171d 3020014726 2020-01-25 2019-09-27 00:00:00 2019-09-27 7 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 39 83 621.3815 M3171d 3020014727 2025-12-08 10:53:10 2024-10-14 8 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 36 67 621.3815 M3171d 3020014724 2026-08-22 11:19:23 2026-08-02 9 2015-03-10 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2015-03-10 1019.00 29 52 621.3815 M3171d 3020014725 2026-11-06 11:35:05 2026-11-04 10 2015-03-10 BK