00795nam a2200241 a 4500 13388 BD-DhGUBL 20250810110907.0 230210s2004 njuad b 001 0 eng d 0471441481 9812531319 DLC DLC DLC BD-DhGUBL 23 621.392 P136d Padmanabhan, T.R. Design Through Verilog HDL / T.R. Padmanabhan, and B. Bala Tripura Sundari. Piscataway ; Hoboken : IEEE Press ; Wiley-Interscience, c 2004. xiii, 455 p. : ills. ; 25 cm. Includes index and bibliographical references (p. 449-450). Computer hardware Verilog System analysis Sundari, B. Bala Tripura Joint author ddc BK 4545 4545 0 0 ddc 0 1 EEE GUBL GUBL REF 2013-10-11 Donated 621.392 P136d 3020013388 2023-02-10 00:00:00 1 2023-02-10 BK