01001nam a2200325 a 4500 BD-DhGUBL 20251119123256.0 201106s2008 maua b 001 0 eng d 9780073380339 0073380334 9780077211646 0077211642 9780070667242 0070667241 (OCoLC)ocm85692907 (OCoLC)85692907 DLC DLC DLC BD-DhGUBL BD-DhGUBL 22 621.392 B8121f Brown, Stephen D Fundamentals of Digital Logic with Verilog Design / Stephen Brown, and Zvonko Vranesic. 2nd ed. New Delhi : Tata McGraw-Hill, c 2008. xix, 865 p. : ills. ; 25 cm. Includes bibliographical references and index. Logic circuits Design and construction Verilog Computer-aided design Vranesic, Zvonko G. Joint author ddc BK 999 999 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 11 27 621.392 B8121f 3020011154 2026-06-06 03:02:01 2026-05-18 1 2013-11-14 BK 0 0 ddc 0 1 EEE GUBL GUBL REF 2013-11-14 0 621.392 B8121f 3020011155 2013-11-14 00:00:00 2 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 9 27 621.392 B8121f 3020011157 2019-03-18 00:00:00 2019-02-13 4 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 9 24 621.392 B8121f 3020011159 2026-08-25 15:02:27 2026-07-06 5 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 5 18 621.392 B8121f 3020011160 2016-01-02 00:00:00 2015-12-23 6 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 9 23 621.392 B8121f 3020011161 2019-03-11 00:00:00 2019-01-29 7 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 11 30 621.392 B8121f 3020011163 2024-07-24 12:43:29 2024-02-12 8 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 15 25 621.392 B8121f 3020011162 2026-07-21 13:30:50 2026-07-06 9 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 8 21 621.392 B8121f 3020011164 2025-05-23 16:44:23 2025-01-21 10 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 8 25 621.392 B8121f 3020011165 2025-05-12 09:05:03 2025-04-19 11 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 16 38 621.392 B8121f 3020011166 2026-02-28 12:02:10 2026-02-17 12 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 11 20 621.392 B8121f 3020011167 2023-01-18 00:00:00 2023-01-03 13 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 5 18 621.392 B8121f 3020011168 2025-02-03 11:51:28 2025-01-21 14 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 11 23 621.392 B8121f 3020011169 2022-10-11 00:00:00 2022-08-31 15 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 12 30 621.392 B8121f 3020011170 2019-03-27 00:00:00 2019-03-21 16 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 12 12 621.392 B8121f 3020011173 2023-05-29 00:00:00 2023-05-15 17 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 7 16 621.392 B8121f 3020011174 2019-08-02 00:00:00 2019-06-28 18 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 9 16 621.392 B8121f 3020011175 2019-11-21 00:00:00 2019-10-30 19 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 5 21 621.392 B8121f 3020011176 2019-04-02 00:00:00 2019-02-26 20 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2013-11-14 10 8 621.392 B8121f 3020011178 2020-11-11 00:00:00 2020-11-05 21 2013-11-14 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2014-10-22 6 22 621.392 B8121f 3020011158 2023-05-15 00:00:00 2022-10-11 22 2014-10-22 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2014-10-22 9 17 621.392 B8121f 3020011172 2019-03-05 00:00:00 2019-03-01 23 2014-10-22 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2014-10-22 10 14 621.392 B8121f 3020011171 2018-06-06 00:00:00 2018-05-15 24 2014-10-22 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2014-10-22 13 23 621.392 B8121f 3020011177 2019-11-15 00:00:00 2019-11-02 25 2014-10-22 BK 0 0 ddc 0 0 EEE GUBL GUBL GEN 2020-01-14 0 621.392 B8121f 3020011156 2020-01-14 00:00:00 3 2020-01-14 BK