| 000 | 00795nam a2200241 a 4500 | ||
|---|---|---|---|
| 001 | 13388 | ||
| 003 | BD-DhGUBL | ||
| 005 | 20250810110907.0 | ||
| 008 | 230210s2004 njuad b 001 0 eng d | ||
| 020 | _a0471441481 | ||
| 020 | _a9812531319 | ||
| 040 |
_aDLC _cDLC _dDLC _dBD-DhGUBL |
||
| 082 | 0 | 0 |
_223 _a621.392 _bP136d |
| 100 | 1 | _aPadmanabhan, T.R. | |
| 245 | 1 | 0 |
_aDesign Through Verilog HDL / _cT.R. Padmanabhan, and B. Bala Tripura Sundari. |
| 260 |
_aPiscataway ; _aHoboken : _bIEEE Press ; _bWiley-Interscience, _cc 2004. |
||
| 300 |
_axiii, 455 p. : _bills. ; _c25 cm. |
||
| 504 | _aIncludes index and bibliographical references (p. 449-450). | ||
| 650 | 0 |
_aComputer hardware _vVerilog |
|
| 650 | 0 | _aSystem analysis | |
| 700 | 1 |
_aSundari, B. Bala Tripura _eJoint author |
|
| 942 |
_2ddc _cBK |
||
| 999 |
_c4545 _d4545 |
||