| 000 | 00749nac a2200229 a 4500 | ||
|---|---|---|---|
| 003 | BD-DhGUBL | ||
| 005 | 20251114101135.0 | ||
| 008 | 250803s2011 uk a|||| |||| 001 0 eng d | ||
| 020 | _a9780470688472 | ||
| 020 | _a9781119995852 | ||
| 040 |
_aBD-DhGUBL _cBD-DhGUBL _dBD-DhGUBL |
||
| 082 |
_222 _a621.3905 |
||
| 100 | _aRushton, Andrew | ||
| 245 |
_aVHDL for Logic Synthesis / _cAndrew Rushton. |
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| 250 | _a3rd ed. | ||
| 260 |
_aWest Sussex, United Kingdom : _bJohn Wiley & Sons, _cc 2011. |
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| 300 |
_axvii, 466 p. : _bill. ; |
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| 500 | _aIncludes index. | ||
| 650 |
_aLogic design _vData processing |
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| 856 |
_uhttps://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/9781119995852?download=true _yClick here to download |
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| 942 |
_2ddc _cEBK |
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| 999 |
_c5007 _d5007 |
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